This invention relates to memory devices such as dynamic random access memories (DRAMs) and, in particular, to a method and apparatus for sensing and/or controlling certain leakage currents associated with memory cells of the DRAM.
To better understand certain problems faced by Applicant, and the inventive resolution of these problems, reference is first made to FIG. 1 which shows a memory array 10 comprised of memory cells 11. For purpose of illustration, the array 10 is shown to have M rows, with one row conductor or word line (WL) per row and to have N columns, with one column conductor or bit line (BL) per column. A memory cell 11 is located at the intersection of each row and column conductor. The row conductors, or word lines, are driven by a row decoder and driver circuit 20 and the column conductors, or bit lines, are driven by a column decoder and driver circuit 30. A write/sense circuit 40 includes circuitry for writing information onto the bit lines for transmission to selected memory cells and circuitry to sense information read from selected memory cells and coupled onto the bit lines.
Generally, in the operation of the memory array of FIG. 1, where the memory cell transistors are N-conductivity type MOS transistors and where the operating potential applied to the memory is VDD volts (e.g., +5 volts) and ground (e.g., zero volts), a word line is activated (selected or enabled) by the application thereto of a "high" voltage (e.g., VDD volts) and the word line is deactivated (not-selected, disabled or in stand-by condition) by the application thereto of a "low" voltage (e.g., zero volts). In FIG. 1, the M word lines of the array 10 are selectively enabled by means of row driver circuit 20 which has M decoder/driver circuits, each of which may be of the type shown in FIG. 2. The decoder driver of FIG. 2 includes a P type transistor, P1, having its source-to-drain path connected between a signal terminal 211 and an output terminal 213 to which is connected its associated word line (WL). The substrate 212 of P1 is connected to a terminal 214 to which is applied a fixed potential (e.g., VDD volts). The source-to-drain paths of transistors N1 and N2 are connected in parallel between output terminal 213, which is connected to a word line (WL), and a terminal 216 to which is applied ground potential. The substrates 217 of N1 and N2 are also returned to ground potential. A first partially decoded signal, RDEC, is applied to the gates of transistors P1 and N1 and a second partially decoded signal, WLD, is applied to signal terminal 211. A signal WLK (typically the inverse of WLD) is applied to the gate of N2 to enable the word line to be selectively clamped to ground for certain input signal conditions.
The circuit of FIG. 2 is used to activate a selected word line. When the signal RDEC is "low" and the signal WLD is a "high" (and WLK is "low"), a "high" is applied to the word line, activating it and enabling the memory cell transistors whose gates are connected to the word line. When the signal RDEC is "high" and/or when the signal WLK is "high", a "low" (e.g., ground) is applied to the word line and it is deemed "deselected" or "deactivated" since the memory cell transistors whose gates are connected to the word line are turned-off. Thus, the circuit of FIG. 2 may be used to apply either an activation (turn-on) voltage (e.g., VDD volts) to the word lines or a deactivation (turn-off) voltage (e.g., zero volts) to the word lines.
The ability to apply a single fixed turn-off voltage is unsatisfactory in certain applications. This is best explained by noting that the memory cells of DRAMs are subject to leakage currents which can destroy the data stored in the memory cells of the DRAM. Therefore, it is necessary to test the cells of a memory array to ensure that their leakage is within acceptable limits. Where, for example, the memory cell transistors are of N-conductivity type, the testing is normally done by first activating the word lines of the memory array by applying a high voltage to them and writing a "high" into the cells by charging their storage capacitors to a high voltage. The word lines are then deactivated by applying zero volts to the word lines for a known period of time. After the known time period has passed the memory cells are selectively read out to determine their data retention. With the circuit of FIG. 2, when a word line is deactivated a single, fixed, turn-off voltage of, for example, zero volts is applied to a word line when it is deselected.
This is unsatisfactory because the leakage of the memory cell transistors varies as a function of the amplitude and polarity of the turn-off voltage applied to their gates, as shown in FIG. 4. Thus, the circuit of FIG. 2 does not permit testing the leakage of the memory cells for different values of turn-off voltage applied to the word lines.
Accordingly, it is an object of this invention to provide circuitry for enabling the application of different values of turn-off voltages to the word lines of a memory array.
It is another object of this invention to sense leakage currents such as the gate induced drain leakage (GIDL) of memory cell transistors for different values of word line voltage.
It is also an object of this invention to determine whether certain turn-off voltages reduce or increase leakage currents such as GIDL.